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HDEval: Benchmarking LLMs that Generate Verilog/Chisel Modules From Natural Language
Hi everyone! I’m Ashwin Bardhwaj, currently pursuing a bachelors in Electrical Engineering and Computer Science at UC Berkeley. I was recently involved in a project to implement a secure hardware encryption enclave in Verilog.
Last updated on Jun 12, 2024
HDEval: Benchmarking LLMs that Generate Verilog/Chisel Modules From Natural Language