llm

Midterm Blogpost: HDEval's LLM Benchmarking for HDL Design
Introduction Hello! My name is Ashwin Bardhwaj, an electrical engineering and computer science student based in San Diego, CA. For the past 6 weeks, I have been working closely with Professor Jose Renau on the HDEval project.
Last updated on Jul 20, 2024
HDEval: Benchmarking LLMs that Generate Verilog/Chisel Modules From Natural Language
Hi everyone! I’m Ashwin Bardhwaj, currently pursuing a bachelors in Electrical Engineering and Computer Science at UC Berkeley. I was recently involved in a project to implement a secure hardware encryption enclave in Verilog.
Last updated on Jun 12, 2024
HDEval: Benchmarking LLMs that Generate Verilog/Chisel Modules From Natural Language